1. Field of the Invention
The present invention relates to a memory circuit comprising a resistive memory element and a method for operating such a memory circuit. The present invention further relates to a memory device in which a resistive memory element is integrated and a method for producing such a device.
2. Description of the Related Art
Memory devices may comprise resistive memory elements for storing information. The resistive memory element can acquire different resistance states each of which may be associated with a logic state. Resistive memory elements are known as CBRAM memory elements (CBRAM: conductive bridging RAM), PMC memory elements (PMC: programmable metallization cell) or other terms may be used. A resistive memory element as understood in the present invention may include a solid state electrolyte which is sandwiched between an anode made from a migrating material and an inert cathode. By applying an electrical field on the solid state electrolyte the migrating material of the anode migrates into the solid state electrolyte rendering the resistive memory element conductive (low resistance) and by applying an inverse electrical field the migrating material is forced back to the anode rendering the resistive memory element non-conductive (high resistance).
Usually, such a kind of memory device has memory cells which include a selection transistor and the resistive memory element which are coupled in series between a plate element providing a fixed potential and a bit line. By activating the selection transistor (rendering the selection transistor conductive) the memory cell can be addressed and the resistive memory element can be accessed by applying a voltage between the bit line and the plate element. In a situation where the selection transistor is non-conductive and the resistive memory element is in a high resistance state, a node between the selection transistor and the resistive memory element is floating. Therefore, it is sensitive to induced disturbances which can be result of level transitions of a signal which is in a close proximity thereto such as an activation signal on a word line by which the respective selection transistor is controlled. Such disturbances may result in an undesired voltage drop over the resistive memory element which can reduce the resistance of the resistive memory element. A change of the resistance of the resistive memory element may result in that the logic state to which the resistance state is associated cannot be detected correctly. Even if the voltage drop over the resistive memory element is not sufficient to program the resistive memory element to a low resistance state, repeated appliance of the voltage drops over the resistive memory element can cause a change in the resistance so that after a plurality of accesses of the respective memory cell the stored information cannot be detected correctly. Consequently, the data retention time depends on the number of access cycles. Even if the stored information can be detected correctly after a change of the resistance of the resistive memory element such a reduction of the resistance may further result in a prolongation of the access time on the memory cell.